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S6B0725A
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Aug. 2001 Ver. 1.5
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate ( board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
S6B0725A Specification Revision History Version 0.0 Initial version 1. VLCD pin: Input or output pin only output pin (page 8, 24) 2001. Regulator resistor select: (1,1,0), (1,1,1) not available (page 27, 38) 2001. VLCD absolute maximum rating:-0.3V to 15V -0.3V to 13V (page 47) 4. X4 voltage boosting VCI range: 2.4V to 3.3V 2.4V to 3.0V (page 48) 5. Power consumption: TBD valid value Oscillator frequency (fCL): (TYP.) 4.75KHz 5.45KHz (page 48) VLCD capacitor is greater than 1F (page 8, 61) 1. Figure 15 is changed (page 27) 2001. Figure 2-1, 2-2 are added (page 14) 2001. Figure 21 is changed (page 43) 4. Table 21 is changed (page 50) 5. Added detail information for several items Added dynamic current consumption at 4 times boosting operation (page 48) Correct some misspellings Content Date 2000.07
1.0
2000.10
1.1 1.2
2000.11 2001.01
1.3
2001.03
1.4 1.5
2001.05 2001.08
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 BLOCK DIAGRAM ......................................................................................................................................... 3 PAD CONFIGURATION ................................................................................................................................. 4 PAD CENTER COORDINATES ...................................................................................................................... 6 PIN DESCRIPTION ........................................................................................................................................ 8 POWER SUPPLY .................................................................................................................................... 8 LCD DRIVER SUPPLY ............................................................................................................................ 8 SYSTEM CONTROL................................................................................................................................ 9 MICROPROCESSOR INTERFACE .........................................................................................................10 LCD DRIVER OUTPUTS .........................................................................................................................12 FUNCTIONAL DESCRIPTION .......................................................................................................................13 MICROPROCESSOR INTERFACE .........................................................................................................13 DISPLAY DATA RAM (DDRAM) ..............................................................................................................18 LCD DISPLAY CIRCUITS .......................................................................................................................21 LCD DRIVER CIRCUITS .........................................................................................................................23 POWER SUPPLY CIRCUITS ..................................................................................................................24 RESET CIRCUIT ....................................................................................................................................30 INSTRUCTION DESCRIPTION ......................................................................................................................31 SPECIFICATIONS .........................................................................................................................................46 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................46 DC CHARACTERISTICS ........................................................................................................................47 AC CHARACTERISTICS .........................................................................................................................50 REFERENCE APPLICATIONS ......................................................................................................................54 MICROPROCESSOR INTERFACE .........................................................................................................54 CONNECTIONS BETWEEN S6B0725A AND LCD PANEL .......................................................................56
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The S6B0725A is a single-chip driver & controller LSI for graphic dot-matrix liquid crystal display systems. This chip can be connected directly to a microprocessor, accepts serial or 8-bit parallel display data from the microprocessor, stores the display data in an on-chip display data RAM of 65 x 104 bits and generates a liquid crystal display drive signal independent of the microprocessor. It provides a high-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. It contains 65 common driver circuits and 104 segment driver circuits, so that a single chip can drive a 65 x 104 dot display. This chip is able to minimize power consumption because it performs display data RAM read/write operation with no external operation clock. In addition, because it contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high-accuracy voltage regulator circuit, low power consumption voltage divider resistors and OP-Amp for liquid crystal driver power voltage, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems.
FEATURES
Display Driver Output Circuits - - - - 65 common outputs and 104 segment outputs
On-chip Display Data RAM Capacity: 65 x 104 = 6,760 bits RAM bit data "1": a dot of display is illuminated RAM bit data "0": a dot of display is not illuminated
Applicable Duty Ratios Duty ratio 1/65 1/55 1/49 1/33 Microprocessor Interface - - - High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series SPI (Serial Peripheral Interface) available. (Only write operation) Applicable LCD bias 1/7 or 1/9 1/6 or 1/8 1/6 or 1/8 1/5 or 1/6 Maximum display area 65 x 104 55 x 104 49 x 104 33 x 104
Various Function Set Display ON / OFF, set initial display line, set page address, set column address, read status, write/read display data, select segment driver output, reverse display ON / OFF, entire display ON / OFF, select LCD bias, set/reset modify-read, select common driver output, control display power circuit, select internal regulator resistor ratio for VLCD voltage regulation, electronic volume, set static indicator state. H/W and S/W Reset available Static drive circuit equipped internally for indicators with 4 flashing mode
- -
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
Built-in Analog Circuit - - - - - - On-chip oscillator circuit for display clock High performance voltage converter (with booster ratios of x3 and x4) High accuracy voltage regulator (temperature coefficient: -0.05 0.03%/C or external input) Electronic contrast control function (64 steps) Vref = 2.1V 3% (VLCD voltage adjustment voltage) High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity)
Operating Voltage Range - - - - - Supply voltage (VDD): 2.4 to 3.6 V LCD driving voltage (VLCD): 4.5 to 9.0 V Operating power: 120 typical (conditions: VDD = 3V, x 3 boosting (VCI = VDD), V0 = 7.6V, Internal power supply ON, display OFF and normal mode is selected) Standby power: 10 maximum (during power save[standby] mode)
Low Power Consumption
Operating Temperatures Wide range of operating temperatures : -40 to 85C
CMOS Process Package Type - Gold bumped chip
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
SEG103 SEG102 SEG101 : : COM31 : COM32 COMS COM63 COM0 COMS SEG2 SEG1 SEG0
:
V DD
33 COMMON DRIVER CIRCUITS VSS
104 SEGMENT DRIVER CIRCUITS
33 COMMON DRIVER CIRCUITS
DISPLAY DATA CONTROL CIRCUIT V/F CIRCUIT PAGE I/O ADDRESS BUFFER CIRCUIT V/R CIRCUIT
COMMON OUTPUT CONTROLLER CIRCUIT
HPMB
VLCD VR INTRS REF VEXT
LINE DISPLAY DATA RAM ADDRES 65 X 104 = 6,760 Bits S CIRCUIT
DISPLAY TIMING GENERATOR CIRCUIT
CL FRS FR
COLUMN ADDRESS CIRCUIT
DUTY0 DUTY1
OSCILLATOR VCI DCDC4B V/C CIRCUIT
STATUS REGISTER BUS HOLDER
INSTRUCTION REGISTER INSTRUCTION DECODER
MPU INTERFACE (PARALLEL & SERIAL)
DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) C68 RESETB PS RW_WRB E_RDB RS CS2 CS1B
Figure 1. Block Diagram
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
PAD CONFIGURATION
240 241 133
- - - - - - - - - - - - - -
Y (0,0)
S6B0725A
(TOP VIEW) X
132
- - - -
274
- - - - - - - - - -
1 98
99
Figure 2. S6B0725A Chip Configuration Table 1. S6B0725A Pad Dimensions Size Pad No. X Y 8220 2540 1 to 98 70 99 to 100 70 100 to 132 60 133 to 134 80 134 to 135 194 135 to 238 68 238 to 239 194 239 to 240 80 241 to 273 60 273 to 274 70 1 to 98 42 92 99 100 to 132 133 to 134 135 to 238 239 to 240 241 to 273 274 All pad 102 102 52 32 52 102 102 52 32 102 102 102 32 52
Item Chip size
Unit
Pad pitch
m
Bumped pad size (Bottom)
Bumped pad height
14 (Typ.)
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
COG Align Key Coordinate
30m 30m 30m 30m 30m 30m
ILB Align Key Coordinate(with Gold Bump *)
42m 108m 42m 108m
30m 30m 30m
(-4008, 1162) 60m
42m
42 m
(4008, 1162)
(-3575, 715)
30m
(3507.85, -597.65)
* When designing COG pattern, ITO pattern must be prohibited on ILB Align Key, DUMMY pads, TEST pads. If ITO pattern is used for routing over these area, it can be happened pattern-short through bumped pattern on these area.
108m
108 m
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m]
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad Name DUMMY1 FRS FR CL TEST1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS TEST2 TEST3 VSS RS VDD DUTY0 VSS DUTY1 VDD PS VSS C68 VDD E_RDB RW_WRB VSS CS1B CS2 VDD VCI VCI VCI X -3390 -3320 -3250 -3180 -3110 -3040 -2970 -2900 -2830 -2760 -2690 -2620 -2550 -2480 -2410 -2340 -2270 -2200 -2130 -2060 -1990 -1920 -1850 -1780 -1710 -1640 -1570 -1500 -1430 -1360 -1290 -1220 -1150 -1080 -1010 -940 -870 -800 -730 -660 -590 -520 -450 -380 -310 -240 -170 -100 -30 40 Y -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 Pad No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name VCI VCI VCI VCI VCI VCI VCI VDD VEXT VSS REF VDD DCDC4B VSS HPMB VDD INTRS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VR VSS TESTA0 TESTB0 VSS VLCD VLCD VLCD VLCD VLCD VLCD TESTA1 TESTB1 TESTA2 TESTB2 TESTA3 TESTB3 TESTA4 TESTB4 RESETB DUMMY2 DUMMY3 COM31 X 110 180 250 320 390 460 530 600 670 740 810 880 950 1020 1090 1160 1230 1300 1370 1440 1510 1580 1650 1720 1790 1860 1930 2000 2070 2140 2210 2280 2350 2420 2490 2560 2630 2700 2770 2840 2910 2980 3050 3120 3190 3260 3330 3400 3963 3963 Y -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1155 -1060 -990 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pad Name COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS DUMMY4 DUMMY5 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 X 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3963 3776 3696 3502 3434 3366 3298 3230 3162 3094 3026 2958 2890 2822 2754 2686 2618 2550 2482 Y -930 -870 -810 -750 -690 -630 -570 -510 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810 870 930 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued) [Unit: m]
Pad No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pad Name SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 X 2414 2346 2278 2210 2142 2074 2006 1938 1870 1802 1734 1666 1598 1530 1462 1394 1326 1258 1190 1122 1054 986 918 850 782 714 646 578 510 442 374 306 238 170 102 34 -34 -102 -170 -238 -306 -374 -442 -510 -578 -646 -714 -782 -850 -918 Y 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 Pad No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Pad Name SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 DUMMY6 DUMMY7 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 X -986 -1054 -1122 -1190 -1258 -1326 -1394 -1462 -1530 -1598 -1666 -1734 -1802 -1870 -1938 -2006 -2074 -2142 -2210 -2278 -2346 -2414 -2482 -2550 -2618 -2686 -2754 -2822 -2890 -2958 -3026 -3094 -3162 -3230 -3298 -3366 -3434 -3502 -3696 -3776 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 Y 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 1117 930 870 810 750 690 630 570 510 450 390 Pad No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 Pad Name COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS DUMMY8 X -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 -3963 Y 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1060
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pins Description Name VDD VSS I/O Supply Supply Power supply Ground Description
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pins Description Name VLCD DCDC4B VR VCI I/O O I I I Description LCD power supply output pin Connect this pin to VSS through capacitor.(Capacitor is greater than 1F) 4 times boosting circuit enable input pin - DCDC4B = "H": 3 times boosting - DCDC4B = "L": 4 times boosting VLCD voltage adjustment pin It is valid only when internal voltage regulator resistors are not used (INTRS = "L"). This is the reference voltage for the voltage converter circuit for the LCD driving. Whether internal voltage converter use or not use, this pin should be fixed. The voltage should have the following range: 2.4V VCI 3.6V This is the external-input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used (REF = "L"). When using internal VREF, this pin is Open Select the external VREF voltage via VEXT pin - REF = "L": using the external VREF - REF = "H": using the internal VREF
VEXT
I
REF
I
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SYSTEM CONTROL
Table 5. System Control Pins Description Name CL FRS FR I/O O O O Display clock output pin Static driver segment output pin This pin is used together with the FR pin. Static driver common output pin This pin is used together with the FRS pin. Internal resistor select pin This pin selects the resistors for adjusting VLCD voltage level. - INTRS = "H": the internal resistors are used - INTRS = "L": the external resistors are used VLCD voltage is controlled by VR pin and external resistive divider. (* refer to page 28) The LCD driver duty ratio depends on the following table. DUTY1 DUTY0 DUTY1 L I L H H DUTY0 L H L H Duty ratio 1/33 1/49 1/55 1/65 Description
INTRS
I
HPMB
I
Power control pin of the power supply circuits for LCD driver. - HPMB = "H": normal mode - HPMB = "L": high power mode
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pins Description Name RESETB I/O I Description Reset input pin When RESETB is "L", initialization is executed. Parallel / Serial data input select input PS H L Interface mode Parallel Serial Chip select CS1B, CS2 CS1B, CS2 Data / instruction RS RS Data DB0 to DB7 SID (DB7) Read / Write E_RDB RW_WRB Write only Serial clock SCLK (DB6)
PS
I
*Note: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RDB and RW_WRB must be fixed to either "H" or "L". Microprocessor interface select input pin - PS = "H", C68 = "H": 6800-series parallel MPU interface - PS = "H", C68 = "L": 8080-series parallel MPU interface - PS = "L", C68 = "H": 4 pin-SPI serial MPU interface - PS = "L", C68 = "L": 3 pin-SPI serial MPU interface Chip select input pins Data/instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data - RS = "L": DB0 to DB7 are control data * This pin must be fixed to either "H" or "L" in case of 3 pin-SPI serial MPU interface mode Read / Write execution control pin C68 H RW_WRB I L 8080-series /WR MPU Type 6800-series RW_WRB RW Description Read / Write control input pin - RW = "H": read - RW = "L": write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal.
C68
I
CS1B CS2
I
RS
I
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Table 6. Microprocessor Interface Pins Description (Continued) Name I/O Read / Write execution control pin C68 MPU Type E_RDB Description Read/Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status. Description
E_RDB
I
H
6800-series
E
L
8080-series
/RD
DB0 to DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L"), - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance. These are pins for chip test. They are set to open.
TESTs
I/O
NOTE: DUMMYs - These pins should be opened (floated).
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
LCD DRIVER OUTPUTS
Table 7. LCD Driver Output Pins Description Name I/O Description LCD segment driver outputs The display data and the FR signal control the output voltage of segment driver. Display data SEG0 to SEG103 H O H L L Power save mode FR H L H L Segment driver output voltage Normal display VLCD VSS V2 V3 VSS Reverse display V2 V3 VLCD VSS VSS
LCD common driver outputs The internal scanning data and FR signal control the output voltage of common driver. Scan data COM0 to COM63 H O H L L Power save mode FR H L H L Common driver output voltage VSS VLCD V1 V4 VSS
COMS
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left open.
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B0725A can interface with an MPU only when CS1B is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_RDB, and RW_WRB inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B0725A has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8. Parallel / Serial Interface Mode PS H Type Parallel CS1B CS1B CS2 CS2 C68 H L H L Interface mode 6800-series MPU mode 8080-series MPU mode 4 pin-SPI serial MPU mode 3 pin-SPI serial MPU mode
L
Serial
CS1B
CS2
Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in table 9. The type of data transfer is determined by signals at RS, E_RDB and RW_WRB as shown in table 10. Table 9. Microprocessor Selection for Parallel Interface C68 H L CS1B CS1B CS1B CS2 CS2 CS2 RS RS RS E_RDB E /RD RW_WRB RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 10. Parallel Data Transfer Common RS H H L L 6800-series E_RDB (E) H H H H RW_WRB (RW) H L H L 8080-series E_RDB (/RD) L H L H RW_WRB (/WR) H L H L Description Display data read out Display data write Register status read Writes to internal register (instruction)
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
CS1B
CS2
RS
RW
E
DB Command Write Data Write Status Read Data Read
Figure 2-1. 6800-Series MPU Interface protocol (PS="H", C68="H")
CS1B CS2 RS /WR /RD DB Command Write Data Write Status Read Data Read
Figure 2-2. 8080-Series MPU Interface Protocol (PS="H", C68="L")
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Serial Interface (PS = "L") When the S6B0725A is active (CS1B="L", CS2="H"), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select (RS) Pin, based on the setting of C68. When the RS pin is used (PS = "H"), data is display data when RS is high, and command data when RS is low. When RS is not used (C68 = "L"), the LCD Driver will receive command from MPU by default. If messages on the data pin are data rather than command, MPU should send Data Direction command (10000000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sending, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. The serial interface type is selected by setting C68 as shown in table 11. Table 11. Parallel / Serial Interface Mode Serial Mode 4 pin SPI serial mode 3 pin SPI serial mode PS L L C68 H L Chip Select CS1B, CS2 CS1B, CS2 Register Select RS pin Software Serial Data / Clock input DB7 / DB6 DB7 / DB6
4 Pin SPI Serial Interface (PS = "L", C68 = "H") In 4-pin serial interface mode, RS pin is used for indicating whether serial data input is display or instruction data. Data is display data when RS is high and instruction data when RS is low.
CS1B CS2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6
SID
SCLK
RS
Figure 3. 4 Pin SPI serial Interface Timing (RS used)
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
3 Pin-SPI Interface (PS = "L", C68 = "L") In 3-Pin SPI Interface mode, the pre-defined instruction called Display Data Length, is used to indicate whether serial data input is display or instruction data instead of RS pin. The data is handled as instruction data until the Display Data Length instruction is issued. This Display Data Length instruction consists of two bytes instruction. The first byte instruction enables the next instruction to be valid, and the data of the second byte indicates that a specified number of display data bytes (1 to 256) are to be transmitted. The next byte after the display data string is handled as instruction data. For details, refers to figure 4.
CS1B / CS2 0 23 0 1 78 15 0 829 830 831
~ ~
~ ~
3 Byte (1) SID
Page
~ ~
2 Byte (2) LSB DDC No. of DATA
~
104 Byte Data In
SCLK
MSB
(1) Set Page and Column Address. Set Page Address : 1 0 1 1 P3 P2 P1 P0 Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0 (2) Set DDC(Data Direction Command) and No. of Data Bytes. Set Data Direction Command( For SPI mode Only): 1 0 0 0000 0 Set No. of Data Bytes(DDL) : D7 D6 D5 D4 D3D2D1D0
Figure 4. 3 Pin SPI Timing (RS is not used) This command is used in 3-Pin SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first. *NOTES: - In spite of transmission of data, if CS1B will be disable, state terminates abnormally. Next state is initialized. - The number of writing display data = DDL register value + 1 Busy Flag The busy flag indicates whether the S6B0725A is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
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S6B0725A
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Data Transfer The S6B0725A uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 5. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signals
RS
/WR
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WR N D(N) D(N+1) D(N+2) D(N+3)
BUS HOLDER
COLUMN ADDRESS
N
N+1
N+2
N+3
Figure 5. Write Timing
MPU signals
RS /WR /RD DB0 to DB7 N Dummy D(N) D(N+1) D(N+2)
Internal signals
/WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3
Figure 6. Read Timing
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 104-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 7 The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD . controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
DB0 DB1 DB2 DB3 DB4
0 1 0 1 0
0 0 1 0 0
1 0 1 1 0
------
0 1 0 0 1
COM0 COM1 COM2 COM3 COM4
-----LCD Display
Display Data RAM
Figure 7. RAM-to-LCD Data Transfer Page Address Circuit
This circuit is for providing a page address to Display Data RAM shown in figure 9. It incorporates 4-bit page address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", but DB2, DB1 and DB0 are "L") is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 9. It incorporates 6-bit line address register changed by only the Initial Display Line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 104-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU cannot access line address of icons.
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Column Address Circuit Column address circuit has a 7-bit preset counter that provides column address to the Display Data RAM as shown in figure 9. When Set Column Address MSB / LSB instruction is issued, 7-bit [Y6:Y0] is updated. And, since this address is increased by 1 each a Read or Write data instruction, microprocessor can access the display data continuously. However, the counter is not increas ed and locked if a non-existing address above 67H. It is unlocked if a column address is set again by set Column Address MSB/LSB instruction. And the column address counter is independent of page address register. ADC Select instruction makes it possible to invert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to the following figure 8. SEG output Column address [Y7:Y0] Display data LCD panel display ( ADC = 0 ) SEG 0 00H 1 SEG 1 01H 0 SEG 2 02H 1 SEG 3 03H 0 ... ... ... ... ... ... SEG 100 64H 1 SEG 101 65H 1 SEG 102 66H 0 SEG 103 67H 0
LCD panel display ( ADC = 1 )
... ...
Figure 8. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
Page Address
DB3 DB2 DB1 DB0
Data
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
0
0
0
0
Page0
1/49 Duty
0
0
0
1
Page1
0
0
1
0
Page2
0
0
1
1
Page3
Start
0
1
0
0
Page4
0
1
0
1
Page5
0
1
1
0
Page6
1
0
0
0
Page8
00 01 02 03 04 05 67 66 65 64 63 62 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
Column Address
ADC=0 ADC=1
-------------
62 63 64 65 66 67 05 04 03 02 01 00 SEG100 SEG101 SEG102 SEG103 SEG98 SEG99
LCD Output
When the initial display line address is 1C[HEX]
Figure 9. Display Data RAM Map
20
1/33 Duty
0
1
1
1
Page7
1/55 Duty
S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
LCD DISPLAY CIRCUITS
Oscillator This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 1 04-bit display data is latched by the display data latch circuit in synchronization with the display clock. The display data which is read to the LCD driver is completely independent of the access to the display data RAM from the microprocessor. The LCD AC signal, FR is generated from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 10.
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
64
65
1
2
3
4
5
6
7
8
9
10
11
12
58
59
60
61
62
63
64
65
1
2
3
4
5
6
CL FR
COM0
VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS
COM1
SEGn
Figure 10. 2-frame AC Driving Waveform (Duty Ratio = 1/65) Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select Instruction specifies the scanning direction of the common output pins. Table 12. The Relationship between Duty Ratio and Common Output Common output pins Duty SHL 0 1 0 1 0 1 0 1 COM [0:15] COM [16:23] COM [24:26] COM [27:36] *NC *NC *NC *NC *NC *NC COM[0:63] COM[63:0] COM [37:39] COM [40:47] COM [48:63] COMS COMS COMS COMS COMS *NC: No Connection
1/33 1/49 1/55 1/65
COM[0:15] COM[31:16] COM[0:23] COM[47:24] COM[0:26] COM[53:27]
COM[16:31] COM[15:0] COM[24:47] COM[23:0] COM[27:53] COM[26:0]
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER CIRCUITS
This driver circuit is configured by 66-channel (including 2 COMS channels) common driver and 1 04-channel segment driver. This LCD panel driver voltage depends on the combination of display data and FR signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD
FR
V SS VLCD V1 V2
COM0
V3 V4 VSS VLCD V1 V2
COM1
V3 V4 V SS VLCD V1 V2
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
COM2
V3 V4 V SS VLCD V1 V2
SEG0
V3 V4 VSS VLCD V1 V2
SEG1
V3 V4 VSS VLCD V1 V2
SEG2
V3 V4 VSS
Figure 11. Segment and Common Timing
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
POWER SUPPLY CIRCUITS
The power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Voltage Converter Circuits These circuits boost up the electric potential between VCI and VSS to 3 or 4 times toward positive side.
VDD VCI VCI
VDD VCI VCI VOUT = 4 x VCI
VOUT = 3 x VCI VDD
DCDC4B DCDC4B
VSS VCI VSS VCI VSS
Figure 12. Three Times Boosting Circuit
Figure 13. Four Times Boosting Circuit
* The VCI voltage range must be set so that the VOUT (Voltage converter output) does not exceed the absolute maximum rating value
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Voltage Regulator Circuits The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, VLCD, by adjusting resistors, Ra and Rb, within the range of |VLCD| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 14, it is necessary to be applied internally. For the Eq. 1, we determine VLCD by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25C is shown in table 13. Rb VLCD = ( 1 + ) x VEV [V] ------ (Eq. 1) Ra (63 - ) VEV = ( 1 - ) x VREF [V] ------ (Eq. 2) 162 Table 13. VREF Voltage at Ta = 25 C REF H L Temp. coefficient -0.05% / C External input VREF [V] 2.1 VEXT
Table 14. Electronic Contrast Control Register (64 Steps) SV5 0 0 : : 1 : : 1 1 SV4 0 0 : : 0 : : 1 1 SV3 0 0 : : 0 : : 1 1 SV2 0 0 : : 0 : : 1 1 SV1 0 0 : : 0 : : 1 1 SV0 0 1 : : 0 : : 0 1 Reference voltage parameter () 0 1 : : 32 (default) : : 62 63 Maximum High : : : : : : : : : : VLCD Minimum Contrast Low
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
REF
VOUT
VEXT
+ V REF V EV
VLCD
Rb VR
INTRS Ra V SS
Inside chip GND
Figure 14. Internal Voltage Regulator Circuit
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between VLCD and VR. We determine VLCD by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15. Internal Rb / Ra ratio depending on 3-bit data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 1 + (Rb / Ra) 3.0 001 3.5 010 4.0 011 4.5 100 5.0 101 5.5 110 Not available 111 Not available
The following figure shows VLCD voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C.
14.00 12.00 10.00 V0 [V] 8.00 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 Electronic volume level
Figure 15. Electronic Volume Level
(1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0)
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between VLCD and VR. Example: For the following requirements 1. LCD driver voltage, VLCD = 6V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 6 = ( 1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 2 (63 - 32) VEV = ( 1 - ) x 2.1 1.698 [V] ------ (Eq. 4) 162 From requirement 3. 6 = 1 [uA] ------ (Eq. 5) Ra + Rb
From equations Eq. 3, 4 and 5 Ra 1.698 [M] Rb 4.302 [M] The following table shows the range of VLCD depending on the above requirements. Table 16. VLCD Depending on Electronic Volume Level Electronic volume level 0 VLCD 4.53 ....... ....... 32 6.00 ....... ....... 63 7.42
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Voltage Follower Circuits VLCD voltage is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are converted by the voltage follower for increasing drive capability. The following table shows the relationship between V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 Level and Duty Ratio Duty ratio 1/33 1/49 DUTY1 L L DUTY0 L H LCD bias 1/5 1/6 1/6 1/8 1/6 1/8 1/7 1/9 V1 (4/5) VLCD (5/6) VLCD (5/6) VLCD (7/8) VLCD (5/6) VLCD (7/8) VLCD (6/7) VLCD (8/9) VLCD V2 (3/5) VLCD (4/6) VLCD (4/6) VLCD (6/8) VLCD (4/6) VLCD (6/8) VLCD (5/7) VLCD (7/9) VLCD V3 (2/5) VLCD (2/6) VLCD (2/6) VLCD (2/8) VLCD (2/6) VLCD (2/8) VLCD (2/7) VLCD (2/9) VLCD V4 (1/5) VLCD (1/6) VLCD (1/6) VLCD (1/8) VLCD (1/6) VLCD (1/8) VLCD (1/7) VLCD (1/9) VLCD
1/55 1/65
H H
L H
High Power Mode The power supply circuit equipped in the S6B0725A for LCD drive has very low power consumption (in normal mode: HPMB = "H"). If use for LCD panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPMB pin to "L"(high power mode) can improve the quality of the display.
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", the initialized driver has following states. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) Serial interface internal register data clear LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/8 (1/49 duty), 1/6 (1/33 duty) On-chip oscillator OFF Power save release Read-modify-write: OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 1, 1) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, the initialized driver has following states. Read-modify-write: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 1, 1) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release While RESETB is "L" or Reset instruction is executed, no instruction except read status could be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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S6B0725A
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 18. Instruction Table x : Don't care Instruction
Display ON / OFF Initial display line Set page address Set column address MSB Set column address LSB Read status Write display data Read display data RS 0 0 0 0 0 0 1 1 RW 0 0 0 0 0 1 0 1 DB7 1 0 1 0 0 BS UY DB6 0 1 0 0 0 ADC DB5 1 ST5 1 0 0 ON/OFF DB4 0 ST4 1 1 0 RESETB DB3 1 ST3 P3 x Y3 0 DB2 1 ST2 P2 Y6 Y2 0 DB1 1 ST1 P1 Y5 Y1 0 DB0 DO N ST0 P0 Y4 Y0 0
Description
Turn ON / OFF LCD panel When DON = 0: display OFF When DON = 1: display ON Specify DDRAM line for COM0 Set page address Set column address MSB Set column address LSB Read the internal status Write data into DDRAM Read data from DDRAM Select SEG output direction When ADC = 0: normal direction (SEG0SEG103) When ADC = 1: reverse direction (SEG103SEG0) Select normal / reverse display When REV = 0: normal display When REV = 1: reverse display Select normal/ entire display ON When EON = 0: normal display. When EON = 1: entire display ON Select LCD bias Set modify-read mode Release modify-read mode Initialize the internal functions Select COM output direction When SHL = 0: normal direction (COM0COM63) When SHL = 1: reverse direction (COM63COM0) Control power circuit operation Select internal resistance ratio of the regulator resistor Set reference voltage mode Set reference voltage register Set static indicator mode Set static indicator register 2-byte Instruction to specify the number of data bytes (SPI Mode) Compound Instruction of display OFF and entire display ON
Write data Read data
ADC select
0
0
1
0
1
0
0
0
0
ADC
Reverse display ON / OFF
0
0
1
0
1
0
0
1
1
REV
Entire display ON / OFF LCD bias select Set modify-read Reset modify-read Reset
0 0 0 0 0
0 0 0 0 0
1 1 1 1 1
0 0 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 1 0
1 0 0 1 0
0 1 0 1 1
EON BIAS 0 0 0
SHL select
0
0
1
1
0
0
SHL
x
x
x
Power control Regulator resistor select Set reference voltage mode Set reference voltage register Set static indicator mode Set static indicator register Set Data Direction & Display Data Length (DDL) Power save
0 0 0 0 0 0 x x -
0 0 0 0 0 0 x x -
0 0 1 x 1 x 1 D7 -
0 0 0 x 0 x 0 D6 -
1 1 0 SV5 1 x 0 D5 -
0 0 0 SV4 0 x 0 D4 -
1 0 0 SV3 1 x 0 D3 -
VC R2 0 SV2 1 x 0 D2 -
VR R1 0 SV1 0 S1 0 D1 -
VF R0 1 SV0 SM S0 0 D0 -
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
Table 18. Instruction Table (Continued) x : Don't care Instruction
NOP Test instruction_1 Test instruction_2 RS 0 0 0 RW 0 0 0 DB7 1 1 1 DB6 1 1 0 DB5 1 1 0 DB4 0 1 1 DB3 0 x x DB2 0 x x DB1 1 x x DB0 1 x x
Description
Non-Operation command Don't use this instruction Don't use this instruction
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
DISPLAY ON / OFF Turns the display ON or OFF RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
0 0 DON = 1: display ON DON = 0: display OFF INITIAL DISPLAY LINE
Sets the line address of display RAM to determine the initial display line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS 0 ST5 0 0 : 1 1 RW 0 ST4 0 0 : 1 1 DB7 0 ST3 0 0 : 1 1 DB6 1 ST2 0 0 : 1 1 DB5 ST5 ST1 0 0 : 1 1 DB4 ST4 ST0 0 1 : 0 1 DB3 ST3 DB2 ST2 DB1 ST1 DB0 ST0
Line address 0 1 : 62 63
SET PAGE ADDRESS Sets the page address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its page address and column address are specified. Along with the column address, the page address defines the address of the display RAM to write or read display data. Changing the page address doesn't effect to the display status. RS 0 P3 0 0 : 0 1 RW 0 DB7 1 P2 0 0 : 1 0 DB6 0 DB5 1 P1 0 0 : 1 0 DB4 1 DB3 P3 P0 0 1 : 1 0 DB2 P2 DB1 P1 Page 0 1 : 7 8 DB0 P0
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
SET COLUMN ADDRESS Sets the column address of display RAM from the microprocessor into the column address register. Along with the column address, the column address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, column addresses are automatically increased. Set Column Address MSB RS 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 x DB2 Y6 DB1 Y5 DB0 Y4
Set Column Address LSB RS RW DB7 0 Y6 0 0 : 1 1 READ STATUS 0 Y5 0 0 : 1 1 0 Y4 0 0 : 0 0
DB6 0 Y3 0 0 : 0 0
DB5 0 Y2 0 0 : 1 1
DB4 0 Y1 0 0 : 1 1
DB3 Y3 Y0 0 1 : 0 1
DB2 Y2
DB1 Y1
DB0 Y0
Column address 0 1 : 102 103
Indicates the internal status of the S6B0725A RS 0 RW 1 DB7 BUSY DB6 ADC DB5 ON / OFF DB4 RESETB DB3 0 DB2 0 DB1 0 DB0 0
Flag BUSY
Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG103 SEG0), 1: normal direction (SEG0 SEG103) Indicates display ON / OFF status. 0: display ON, 1: display OFF Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: chip is being reset
ADC ON / OFF RESETB
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S6B0725A
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
WRITE DISPLAY DATA 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data
Set Page Address Set Column Address Data write Column = Column + 1 YES
Set Page Address Set Column Address Dummy Data Read Column = Column + 1 Data Read Column = Column + 1 YES
Data Write Continue ? NO Optional Status
Data Read Continue ? NO Optional Status
Figure 16. Sequence for Writing Display Data Read Display Data
Figure 17. Sequence for Reading Display Data
8-bit data from display data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read data
ADC SELECT (SEGMENT DRIVER DIRECTION SELECT) Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
ADC = 0: normal direction (SEG0 SEG103) ADC = 1: reverse direction (SEG103 SEG0)
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
REVERSE DISPLAY ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 REV 0 (normal) 1 (reverse) ENTIRE DISPLAY ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display On/Off instruction. RS RW DB7 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
RAM bit data = "1" LCD pixel is illuminated LCD pixel is not illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
0 0 1 EON = 0: normal display EON = 1: entire display ON SELECT LCD BIAS
Selects LCD bias ratio of the voltage required for driving the LCD. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 Bias
Duty ratio 1/33 1/49 1/55 1/65
DUTY1 0 0 1 1
DUTY0 0 1 0 1
LCD bias Bias = 0 1/6 1/8 1/8 1/9 Bias = 1 1/5 1/6 1/6 1/7
SET MODIFY-READ This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
RESET MODIFY-READ This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify-read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write NO Change Complete ? YES Reset Modify-Read Return Column Address (N)
Figure 18. Sequence for Cursor Display RESET This instruction resets initial display line, column address, page address, and common output status select to their initial status, but does not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
SHL SELECT (COMMON OUTPUT MODE SELECT) COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x x : Don't care
SHL = 0: normal direction (COM0 COM63) SHL = 1: reverse direction (COM63 COM0) POWER CONTROL
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON
0 1 0 1 REGULATOR RESISTOR SELECT
Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the Table 15. RS 0 R2 0 0 0 0 1 1 1 1 RW 0 R1 0 0 1 1 0 0 1 1 DB7 0 R0 0 1 0 1 0 1 0 1 DB6 0 DB5 1 DB4 0 DB3 0 (1 + Rb / Ra) ratio 3.0 3.5 4.0 4.5 (default) 5.0 5.5 Not available Not available DB2 R2 DB1 R1 DB0 R0
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S6B0725A
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
REFERENCE VOLTAGE SELECT Consists of 2-byte instruction. The 1 instruction sets reference voltage mode, the 2 one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. The 1 Instruction: Set Reference Voltage Select Mode RS 0 The 2
nd st st nd
RW 0
DB7 1
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 1
Instruction: Set Reference Voltage Register RW 0 DB7 x DB6 x DB5 SV5 DB4 SV4 DB3 SV3 DB2 SV2 DB1 SV1 DB0 SV0
RS 0
SV5 0 0 : : 1 : : 1 1
SV4 0 0 : : 0 : : 1 1
SV3 0 0 : : 0 : : 1 1
SV2 0 0 : : 0 : : 1 1
SV1 0 0 : : 0 : : 1 1
SV0 0 1 : : 0 : : 0 1
Reference voltage parameter () 0 1 : : 32 (default) : : 62 63
V0 Minimum : : : : : Maximum
Contrast Low : : : : : High
Setting Reference Voltage Start 1st Instruction for Mode Setting
nd
2 Instruction for Register Setting Setting Reference Voltage End
Figure 19. Sequence for Setting the Reference Voltage
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
SET STATIC INDICATOR STATE Consists of two bytes instruction. The first byte instruction (Set Static Indicator Mode) enables the second byte instruction (Set Static Indicator Register) to be valid. The first byte sets the static indicator on/off. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. The 1 Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 0 DB0 SM 0 0 1 SM = 0: static indicator OFF SM = 1: static indicator ON The 2
nd st
Instruction: Set Static Indicator Register RW 0 S1 0 0 1 1 DB7 x S0 0 1 0 1 DB6 x DB5 x DB4 x DB3 x DB2 x DB1 S1 DB0 S0
RS 0
Status of static indicator output OFF ON (about 1 second blinking) ON (about 0.5 second blinking) ON (always ON)
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S6B0725A
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SET DATA DIRECTION & DISPLAY DATA LENGTH (3-PIN SPI MODE) Consists of two bytes instruction. This command is used in 3-Pin SPI mode only (PS = "L" and C68 = "L"). It will be two continuous commands, the first byte control the data direction (write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When RS is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. The 1 Instruction: Set Data Direction (Only Write Mode) RS x The 2 x
nd st
RW x
DB7 1
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
Instruction: Set Display Data Length (DDL) Register RW x DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
RS
D7 0 0 0 : 1 1 1 NOP
D6 0 0 0 : 1 1 1
D5 0 0 0 : 1 1 1
D4 0 0 0 : 1 1 1
D3 0 0 0 : 1 1 1
D2 0 0 0 : 1 1 1
D1 0 0 1 : 0 1 1
D0 0 1 0 : 1 0 1
Display Data Length 1 2 3 : 254 255 256
Non-Operation Instruction RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
TEST INSTRUCTION (TEST INSTRUCTION_1 & TEST INSTRUCTION_2) These are the instruction for IC chip testing. Please do not use it. If the test instruction is used by accident, it can be cleared by applying "0" signal to the RESETB input pin or the reset instruction. RS 0 0 RW 0 0 DB7 1 1 DB6 1 0 DB5 1 0 DB4 1 1 DB3 x x DB2 x x DB1 x x DB0 x x
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
POWER SAVE (COMPOUND INSRTUCTION) If the entire display ON / OFF instruction is issued during the display OFF state, S6B0725A enters the power save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one mode of sleep and standby mode. When Static Indicator mode is ON, standby mode is issued. When OFF, sleep mode is issued. Power save mode is released by the entire display OFF instruction.
Static Indicator OFF
Static Indicator ON
Power Save (Compound Instruction) [Display OFF] [Entire Display ON] Sleep Mode [Oscillator Circuit: OFF] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: <2uA] Standby Mode [Oscillator Circuit: ON] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: <10uA]
Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] 2 Bytes Command
Power Save OFF [Entire Display OFF]
Release Sleep Mode
Release Standby Mode
Figure 20. Power Save (Compound Instruction) - Sleep Mode This stops all operations in the LCD display system, and as long as there are no access from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: a. The oscillator circuit and the LCD power supply circuit are halted. b. All liquid crystal drive circuits are halted, and the segment and common outputs go to the VSS level. - Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate. b. The duty drive system liquid crystal drive circuits are halted and the segment and common outputs go to the VSS level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode.
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
REFERENTIAL INSTRUCTION SETUP FLOW (1)
User System Setup by External Pins
Start of Initialization
Power ON (V DD - VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User LCD Power Setup by Internal Instructions [Voltage Converter ON] Waiting for 25ms User LCD Power Setup by Internal Instructions [Voltage Regulator ON] Waiting for 1ms User LCD Power Setup by Internal Instructions [Voltage Follower ON]
User LCD Power Setup by Internal Instructions [Regulator Resistor Select] [Reference Voltage Register Set]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 21. Initializing with the Built-in Power Supply Circuits
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
REFERENTIAL INSTRUCTION SETUP FLOW (2)
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Initial Display Data
Turn Display ON by Instruction [Display ON / OFF: DON = 1 ]
End of Data Display
Figure 22. Data Displaying
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
REFERENTIAL INSTRUCTION SETUP FLOW (3)
Optional Status
Turn Display OFF by Instruction [Display OFF]
Turn Off the Voltage Regulator by Internal Instructions [Voltage Regulator OFF] Waiting for 50ms Turn Off the Voltage Follower by Internal Instructions [Voltage Follower OFF] Waiting for 1ms Turn Off the Voltage Converter by Internal Instructions [Voltage Converter OFF] Waiting for 1ms Power OFF (VDD - VSS)
Figure 23. Power OFF
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings Parameter Supply voltage range Input voltage range Operating temperature range Storage temperature range Symbol VDD VLCD VIN TOPR TSTR Rating - 0.3 to +7.0 - 0.3 to +13.0 - 0.3 to VDD + 0.3 - 40 to +85 - 55 to +125 Unit V V V C C
Notes: 1. VDD and VLCD are based on VSS = 0V. 2. Voltages VLCD V1 V2 V3 V4 VSS must always be satisfied. 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
DC CHARACTERISTICS
Table 20. DC Characteristics (VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85C) Item Operating voltage (1) LCD power voltage (2) Input voltage Output voltage High Low High Low Symbol VDD VLCD VIH VIL VOH VOL IIL IOZ RON fOSC fCL VCI VREF Ta = 25C IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C Duty ratio = 1/65 x3 x4 - 0.05%/C Condition Min. 2.4 4.5 0.8VDD VSS 0.8VDD VSS - 1.0 - 3.0 32.7 4.09 2.4 2.4 2.04 Typ. 2.0 43.6 5.45 2.1 Max. 3.6 9.0 VDD 0.2VDD VDD 0.2VDD + 1.0 + 3.0 3.0 54.5 6.81 3.6 3.0 2.16 A A k KHz *5 *6 SEGn COMn *7 CL *8 V *4 Unit V V V Pin used VDD *1 VLCD *2 *3
Input leakage current Output leakage current LCD driver ON resistance Oscillator frequency Internal External
Voltage converter Input voltage Reference voltage
V V
VCI *9
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
Dynamic Current Consumption when the Built-in Power Circuit is ON (At Operate Mode) (Ta = 25C) Item Symbol Condition VDD = 3.0V, (VCI = VDD, 3 times boosting) V0 - VSS = 7.64V, 1/65 duty ratio, Display pattern OFF, Normal power mode VDD = 3.0V, (VCI = VDD, 3 times boosting) V0 - VSS = 7.64V, 1/65 duty ratio, Display pattern checker, Normal power mode VDD = 3.0V, (VCI = VDD, 4 times boosting) V0 - VSS = 8.40V, 1/65 duty ratio, Display pattern OFF, Normal power mode VDD = 3.0V, (VCI = VDD, 4 times boosting) V0 - VSS = 8.40V, 1/65 duty ratio, Display pattern checker, Normal power mode Min. Typ. Max. Unit Pin used
-
120
-
*11
-
140
-
*11
Dynamic current consumption (2)
IDD2
-
180
-
*11
-
200
-
*11
Current Consumption during Power Save Mode (Ta = 25C) Item Sleep mode current Standby mode current Symbol IDDS1 IDDS2 Condition During sleep During standby Min. Typ. Max. 2 10 Unit A A Pin used
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Table 21. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio 1/65 1/55 Item On-chip oscillator circuit is used On-chip oscillator circuit is used On-chip oscillator circuit is used On-chip oscillator circuit is used
fCL
fOSC
fFR
fOSC 2 x 8 x 65 fOSC 2 x 9 x 55 fOSC
--
8 fOSC
9 fOSC
1/49
10 fOSC
2 x 10 x 49 fOSC
1/33
15 2 x 15 x 33 (fOSC: oscillation frequency, fCL: display clock frequency, fFR: LCD AC signal frequency)
[* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RDB, RW_WRB, RESETB, C68, PS, INTRS, HPMB pins. *4. DB0 to DB7, FR, FRS, CL pins. *5. CS1B, CS2, RS, DB[7:0], E_RDB, RW_WRB, RESETB, C68, PS, INTRS, HPMB pins. *6. Applies when the DB[7:0], FR, FRS and CL pins are in high impedance. *7. Resistance value when 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON = V / 0.1 [k] (V: voltage change when 0.1[mA] is applied in the ON status.) *8. See table 21 for the relationship between oscillation frequency and frame frequency. *9. On-chip reference voltage source of the voltage regulator circuit to adjust VLCD. *10,11. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS tAS80 CS1B (CS2) tPW L80(R), RDB, WRB 0.9V DD 0.1V DD tDS80 DB0 to DB7 (Write) tACC80 DB0 to DB7 (Read) ** tPWL80(W) and tPWL80(R) is specified in the overlapped period when CS1B is low (CS2 is high) and WRB(RDB) is low. tOD80 tPWL80(W) tPWH80(R), tDH80 tPWH80(W) tAH80
tCY80
Figure 24. Read / Write Characteristics (8080-series MPU) (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Max. Unit Remark 140 100 ns ns ns ns ns ns CL = 100 pF
Item Address setup time Address hold time System cycle time Pulse width (WRB) Pulse width (RDB) Data setup time Data hold time Read access time Output disable time
Signal RS RS RW_WRB E_RDB DB7 to DB0
Symbol tAS80 tAH80 tCY80 tPWL80 (W) tPWH80 (W) tPWL80 (R) tPWH80 (R) tDS80 tDH80 tACC80 tOD80
Min. 0 0 300 60 60 60 60 40 15 10
Typ. -
Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < (tCY80 - tPWL80 (W) - tPWH80 (W) ) for write, (tr + tf) < (tCY80 - tPWL80 (R) - tPWH80 (R)) for read
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Read / Write Characteristics (6800-series Microprocessor)
RS RW tAS68 CS1B (CS2) tPW H68(R), E 0.1V DD 0.9V DD tDS68 DB0 to DB7 (Write) tACC68 DB0 to DB7 (Read) tOD68 tDH68 tPW H68(W) tPW L68(R), tPW L68(W) tAH68
tCY68
** tPWH68(W) and tPWH68(R) is specified in the overlapped period when CS1B is low (CS2 is high) and E is high. Figure 25. Read / Write Characteristics (6800-series Microprocessor) (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Max. Unit Remark 140 100 ns ns ns ns CL = 100 pF
Item Address setup time Address hold time System cycle time Data setup time Data hold time Access time Output disable time Enable pulse width Read
Signal RS RW RS DB7 to DB0
Symbol tAS68 tAH68 tCY68 tDS68 tDH68 tACC68 tOD68 tPWH68(R) tPWL68(R) tPWH68(W) tPWL68(W)
Min. 0 0 300 40 15 10 120 120 60 60
Typ. -
E_RDB Write
-
ns
Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less. (tr + tf) < (tCY68 - tPWH68 (W) - tPWH68 (W) ) for write, (tr + tf) < (tCY80 - tPWH68 (R) - tPWL68 (R)) for read
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
Serial Interface Characteristics
tCSS CS1B (CS2)
tCHS
tASS
tAHS
RS 0.9VDD DB6 (SCLK) 0.1VDD tWLS tDSS
tCYS
tWHS tDHS
DB7 (SID)
Figure 26. Serial Interface Characteristics (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Max. Unit Remark ns
Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CS1B setup time CS1B hold time
Signal DB6 (SCLK) RS DB7 (SID) CS1B
Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS
Min. 250 100 100 150 150 100 100 150 150
Typ. -
ns ns ns
Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less.
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S6B0725A
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Reset Input Timing
tRW RESETB tR Internal status During reset Reset complete
Figure 27. Reset Input Timing (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Remark Max. Unit 1.0 s s
Item Reset low pulse width Reset time
Signal RESETB -
Symbol tRW tR
Min. 1.0 -
Typ. -
Display Control Output Timing tDFR CL (OUT) FR
Figure 28. Display Control Output Timing (VDD = 2.4 to 3.6V, Ta = -40 to +85C) Item FR delay time Signal FR Symbol tDFR Min. Typ. 20 Max. 80 Unit ns Remark CL = 50 pF
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
In Case of Interfacing with 6800-series (PS = "H", C68 = "H")
CS1B CS2
6800-series MPU
RS E RW DB0 to DB7 RESETB VDD VDD
CS1B CS2 RS E_RDB
S6B0725
RW_WRB DB0 to DB7 RESETB C68 PS
Figure 29. Interfacing with 6800-series In Case of Interfacing with 8080-series (PS = "H", C68 = "L") CS1B CS2 RS RDB WRB DB0 to DB7 RESETB VSS VDD
8080-series MPU
CS1B CS2 RS S6B0725 E_RDB RW_WRB DB0 to DB7 RESETB C68 PS
Figure 30. Interfacing with 8080-series
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S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
In Case of Serial Interface with RS Pin (PS = "L", C68 = "H ") CS1B CS2 RS SID SCLK RESETB OPEN VDD VSS
MPU
CS1B CS2 RS S6B0725 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 C68 PS
Figure 31. 4 Pin Serial Interface In Case of Serial Interface with Software Command (PS = "L", C68 = "L ") CS1B CS2 VSS or VDD SID SCLK RESETB OPEN VSS VSS
MPU
CS1B CS2 RS S6B0725 DB7(SID) DB6(SCLK) RESETB DB0 to DB5 C68 PS
Figure 32. 3 Pin SPI Serial Interface
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104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
CONNECTIONS BETWEEN S6B0725A AND LCD PANEL
Single Chip Structure (1/65 Duty Configurations)
(R)
(R)
64 x 104 pixels
(R)
64 x 104 pixels
(R)
SEG0
COMS COM0 : COM31
...........
SEG103
COM32 : COM63 COMS
SEG103
COM3 2 : COM6 3 COMS
...........
SEG0
COMS COM0 : COM31
S6B0725 (Bottom View)
S6B0725 (Top View)
Figure 33. SHL = 1, ADC = 0
Figure 34. SHL = 1, ADC = 1
COM31 : COM0 COMS
S6B0725 (Top View)
...........
COMS COM63 : COM32
COMS COM63 : COM32
S6B0725 (Bottom View)
............
COM31 : COM0 COMS
SEG0
SEG103
SEG103
SEG0
(R)
(R)
64 x 104 pixels
(R)
64 x 104 pixels
(R)
Figure 35. SHL = 0, ADC = 0
Figure 36. SHL = 0, ADC = 1
56
S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Single Chip Structure (1/55 Duty Configurations)
(R)
(R)
54 x 104 pixels
(R)
54 x 104 pixels
(R)
SEG0
COMS COM0 : COM26
...........
SEG103
COM37 : COM63 COMS
SEG103
COM37 : COM63 COMS
...........
SEG0
COMS COM0 : COM26
S6B0725 (Bottom View)
S6B0725 (Top View)
Figure 37. SHL = 1, ADC = 0
Figure 38. SHL = 1, ADC = 1
COM26 : COM0 COMS
S6B0725 (Top View)
...........
COMS COM63 : COM37
COMS COM63 : COM37
S6B0725 (Bottom View)
............
COM26 : COM0 COMS
SEG0
SEG103
SEG103
SEG0
(R)
(R)
54 x 104 pixels
(R)
54 x 104 pixels
(R)
Figure 39. SHL = 0, ADC = 0
Figure 40. SHL = 0, ADC = 1
57
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
Single Chip Structure (1/49 Duty Configurations)
(R)
(R)
48 x 104 pixels
(R)
48 x 104 pixels
(R)
SEG0
COMS COM0 : COM23
...........
SEG103
COM40 : COM63 COMS
SEG103
COM40 : COM6 3 COMS
...........
SEG0
COMS COM0 : COM23
S6B0725 (Bottom View)
S6B0725 (Top View)
Figure 41. SHL = 1, ADC = 0
Figure 42. SHL = 1, ADC = 1
COM23 : COM0 COMS
S6B0725 (Top View)
...........
COMS COM63 : COM40
COMS COM63 : COM40
S6B0725 (Bottom View)
............
COM23 : COM0 COMS
SEG0
SEG103
SEG103
SEG0
(R)
(R)
48 x 104 pixels
(R)
48 x 104 pixels
(R)
Figure 43. SHL = 0, ADC = 0
Figure 44. SHL = 0, ADC = 1
58
S6B0725A
SPEC. VER. 1.5
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Single Chip Structure (1/33 Duty Configurations)
(R)
(R)
32 x 104 pixels
(R)
32 x 104 pixels
(R)
SEG0
COMS COM0 : COM15
...........
SEG103
COM48 : COM63 COMS
SEG103
COM48 : COM6 3 COMS
...........
SEG0
COMS COM0 : COM15
S6B0725 (Bottom View)
S6B0725 (Top View)
Figure 45. SHL = 1, ADC = 0
Figure 46. SHL = 1, ADC = 1
COM15 : COM0 COMS
S6B0725 (Top View)
...........
COMS COM63 : COM48
COMS COM63 : COM48
S6B0725 (Bottom View)
............
COM15 : COM0 COMS
SEG0
SEG103
SEG103
SEG0
(R)
(R)
32 x 104 pixels
(R)
32 x 104 pixels
(R)
Figure 47. SHL = 0, ADC = 0
Figure 48. SHL = 0, ADC = 1
59
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
SPEC. VER. 1.5
S6B0725A
S6B0725A Application Circuit for Serial Mode n 4 Pin SPI Serial Interface
VCC
C1 -+
LCD MODULE
VCC PORT4 PORT3 PORT1 PORT0
GND
VLCD V DD VCI SCLK COM[0:64] SID RS CS1B
COMMONS
MPU
RESET GND
S6B0725A
SEG[0:103] RESETB V SS SEGMENTS
LCD PANEL
GND
* C1 is greater than 1 F
Figure 49. S6B0725A Application Circuit for 4 Pin SPI Serial Interface
60

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